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MCP6S21/2/6/8
4.2.2
RAIL-TO-RAIL INPUT
4.3
Resistor Ladder
The input stage of the internal op amp uses two differ-
ential input stages in parallel; one operates at low V IN
(input voltage), while the other operates at high V IN .
With this topology, the internal inputs can operate to
0.3V past either supply rail. The input offset voltage is
measured at both V IN = V SS - 0.3V and V DD + 0.3V to
ensure proper operation.
The transition between the two input stages occurs
when V IN ≈ V DD - 1.5V. For the best distortion and gain
linearity, avoid this region of operation.
The resistor ladder shown in Figure 4-1 (R LAD = R F +
R G ) sets the gain. Placing the gain switches in series
with the inverting input reduces the parasitic capaci-
tance, distortion and gain mismatch.
R LAD is an additional load on the output of the PGA and
causes additional current draw from the supplies.
In Shutdown mode, R LAD is still attached to the OUT
and V REF pins. Thus, these pins and the internal ampli-
fier ’s inverting input are all connected through R LAD
and the output is not high-Z (unlike the external op
4.2.3
RAIL-TO-RAIL OUTPUT
amp).
The Maximum Output Voltage Swing is the maximum
swing possible under a particular output load. Accord-
ing to the specification table, the output can reach
within 60 mV of either supply rail when R L = 10 k ? and
V REF = V DD /2. See Figure 2-21 for typical performance
under other conditions.
While R LAD contributes to the output noise, its effect is
small. Refer to Figure 2-12.
4.4 Shutdown Mode
These PGAs use a software shutdown command.
When the SPI interface sends a shutdown command,
the internal op amp is shut down and its output placed
4.2.4
INPUT VOLTAGE AND PHASE
in a high-Z state.
REVERSAL
The amplifier family is designed with CMOS input
devices. It is designed to not exhibit phase inversion
when the input pins exceed the supply voltages.
Figure 2-34 shows an input voltage exceeding both
supplies with no resulting phase inversion.
The maximum voltage that can be applied to the input
pins (CHX) is V SS - 0.3V to V DD + 0.3V. Voltages on the
inputs that exceed this absolute maximum rating can
cause excessive current to flow in or out of the input
pins. Current beyond ±2 mA can cause possible reli-
ability problems. Applications that exceed this rating
must be externally limited with an input resistor, as
shown in Figure 4-2.
R IN CHX
The resistive ladder is always connected between
V REF and V OUT ; even in shutdown. This means that the
output resistance will be on the order of 5 k ? and there
will be a path for output signals to appear at the input.
The Power-on Reset (POR) circuitry will temporarily
place the part in shutdown when activated. See
Section 5.4, “Power-On Reset”, for details.
R IN ≥ -------------------------------------------------------------------------------
V SS – ( Minimum expected V IN )
R IN ≥ ----------------------------------------------------------------------------
V IN
MCP6S2X
( Maximum expected V IN ) – V DD
2 mA
2 mA
V OUT
FIGURE 4-2:
into an input pin.
R IN limits the current flow
? 2003 Microchip Technology Inc.
DS21117A-page 17
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